Non-volatile data storage devices, such as universal serial bus (USB) flash memory devices or removable storage cards, have allowed for increased portability of data and software applications. Flash memory devices can enhance data storage density by storing multiple bits in each flash memory cell. For example, Multi-Level Cell (MLC) flash memory devices provide increased storage density by storing 3 bits per cell, 4 bits per cell, or more. Although increasing the number of bits per cell and reducing device feature dimensions may increase a storage density of a memory device, a bit error rate of data stored at the memory device may also increase.
Random input/output operations per second (IOPS) performance has become one of the criteria by which memory products such as iNAND are compared. Page based Flash Management (FM) can improve performance during programming (e.g., for large number of programming IOPS). However, issuing Control Reads (CR) prior to data reads can reduce read performance when page based Flash Management is used.
For example, a CR may be used to identify a physical address of the data in the memory. The physical address may be stored in a logical-to-physical address mapping table in the memory. The logical-to-physical address mapping table may be too large (e.g. 1 MB table size per 1 GB of memory) to be kept as a whole at a controller of a flash memory device. As a result, during random read operations over a large span of read addresses, whenever a portion of the logical-to-physical address mapping table including a requested address is not cached in the controller, a CR may be issued to read the logical-to-physical address mapping table from the memory, resulting in increased overall read latency and reduced number of IOPS.